Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi jbeniston, thanks for the reply. Can you pls explain this in detail.. ? how the cell structure will be and the connection of these cells with other std cells.
Hi artmalik, It's good explanation thank you. As said "threshold voltage decreases Leakage increases" why does this happen..? how Vt and leakage are related.?
Yeah these have been implemented in Matlab and have got good results also.. now need to be implemented on hardware(virtex5 board) so i have chosen system generator but now stuck up with the designing part.. if u have any idea pls help me regarding this..
thank you.
Firstly thank you for the reply.. yeah I have seen those demos but if i get some demos or tutorials specific to my problem it will be helpful for example filter design or classifier design.
Hi,
Im new to system generator, need to implement image processing algorithms like filtering using median filter and classification by kNN classifier on vertex5 board. can you please refer some tutorials other than system generator user guide. how to make use of system generator blocks in my...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
