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Recent content by deepamj

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    [SOLVED] 100% Repair Of Laptop & Desktop Motherboard

    i've asus eeepc having windows xp(no cd/dvd drives) with recovery disc.how can i format the netbook and reinstall the Os without external cd/dvd drive? i think it is not possible to copy the contents of recovery disc to pen drive. pl help
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    profiling vhdl - profiler is not giving details of functions

    profiling vhdl i've attached vhdl design as peripheral in edk. the 'main' of application software includes only functions like- XGpio_DiscreteWrite,XGpio_SetDataDirection,XGpio_Initialize, _mWriteSlaveReg0,_mReadSlaveReg0,... no standard C functions. the profiler is not giving details of...
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    Input from HyperTerminal to Microblaze using RS232

    hi try to add the header file manually from projectdirectory\drivers\src\*.h. i don't know whether it will be the correct method
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    ISE 10.1 and ISE 11.3 optimization properties difference

    when vhdl code is synthesised in ise 10.1, "warning:xst:2677 --signal of sequntial type unconnected in entity block" were there and the post synthesis simulation result did not match behavioral simulation. on synthesizing the same code in ise 11.3 most of the xst2677 warnings were not there...
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    [SOLVED] 100% Repair Of Laptop & Desktop Motherboard

    original multimedia CDs shown as blank in laptop i've compaq presario laptop. from one morning it started showing some multimedia CDs(original CDs,not pirate) as blank which were running previously on the same laptop(some other CDs are running smoothly). the same CDs are running on other...
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    reduce resource utilization - aes fpga

    helo tiksan thank you for the reply. i'm newbie in fpga. can u elaborate what's meant by "mapping LUTs to RAMs" and 10,20,40....clk cycle core. .it will be helpful hopes for a reply
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    reduce resource utilization - aes fpga

    i hav vhdl code for aes encryption/decryption which runs fine during behavioral simulation. most parts of the algorithm are implemented using look up tables. the synthesis went on running................... after a day's wait it got synthesised, but slice LUTs were overutilized. similar to...
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    EDK TooLs PLEASE HELP ME OUT?

    dear ravikant i'm also doing similar project based on microblaze. my aim is to implement the time critical portions in aes algorithm and to compare the speed advantage obtained from pure software version. can u give me some guidance in how to proceed . hopes for a reply deepa
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    hardware accelerators in microblaze virtex5

    microblaze in virtex 5 fpga from where can i get more information regarding : # Partitioning the application such that some portions will be compiled for use on the microblaze processor and other portions will be implemented in the FPGA. # Actually getting those portions of the application that...

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