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Recent content by deepak242003

  1. deepak242003

    what are Tap layers in Tap cells?

    reading basic fabrication techniques will answer this question. BTW tap cell will need AA contact and metal and well in case of well contact .
  2. deepak242003

    Which layout configuration?

    I will prefer the left one. With more drain fingers it will support more currents. But again it will be case by case basis.
  3. deepak242003

    Where we can connect the dummies in this diiferential pair matching?

    i)bulk can go to source connection of matched pair with G,D,S going to VDD!. ii)I believe we dont share diffusions in lower technology . (STI effect )
  4. deepak242003

    Triple guard ring for ESD

    Re:NPN/ Triple guard ring for ESD I meaned n type then p type and again n type. I guess N and P should be sufficient to take of majority and minority carrier injection ..
  5. deepak242003

    getting antenna violation

    Thats correct . This is what suggested by "VLSI_Learner " . First check which metal is giving antenna and add jumper of next higher metal as near to gate as possible . Hopefully this should resolve .
  6. deepak242003

    Triple guard ring for ESD

    Why triple guardring is required for ESD transistor ?. Any supporting article will be of great help .:-o
  7. deepak242003

    Layer Density Rules_Thermal Conductivity

    They all varies from process to process .. It is adviced to get those inform from design rule document(DRD).
  8. deepak242003

    Difference between n-well and high voltage n-well

    Thanks Erikl for the explanation . It is really interesting for me to understand this in more detail . I tried searching the mentioned book ,but cant find the free ebook version .. It will be great help if you have that book handy or similar papers and upload it here ... :)
  9. deepak242003

    doping concentration of high voltage nwell

    Hi, can anybody help with the doping concentration of high voltage N-Well with respect to N well . Any document refering to its effect on device breakdwon will help a lot... Deepak
  10. deepak242003

    Difference between n-well and high voltage n-well

    Hi Erik, Can you please help with understanding why WHN is low doped with respect to NW ? Any supporting document will be more than help . THanks Deepak.
  11. deepak242003

    unbound pin in assura LVS

    which layer u r using for labels?
  12. deepak242003

    DRC Error - AMIS05 PDK - Metal1 Density Error < 30%

    Three options : 1) Foudry will fill it for you .. You can ignore this error at this stage. 2) Some internal scripts to fill the density . Check with CAD teams. 3) Manual Fill : Dummy metal Pcells ( internal to your organisation ) might be available . Hope this will help. :)
  13. deepak242003

    What is the DNW layer in tsmc090 ?

    Re: tsmc090 layers DNW is deep n well active layer : DIFF
  14. deepak242003

    How to import display.drf to Calibre

    1) create new library in library manager 2) attach it to the techfile ( you can get this path from cad team.). It will prompt for this when u ll create new lib. 3) give this lib path while importing you gds. let me know if any issues. Deepak
  15. deepak242003

    DRC using calibre in umc90nm

    bcoz .cal file is required only for calibre verification.. not assura...;)
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