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deathblow

Recent content by deathblow

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How to reduce the no of Embeded mults and LUT's in simuilink xilinx blockset?

Thanks sir TrickyDicky. I have redesign the the algo. But as you mention the latency and accuracy problem. i would require some more help.
- deathblow
- Post #3
- Apr 26, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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How to reduce the no of Embeded mults and LUT's in simuilink xilinx blockset?

Hi I have implemented canny and HD distance algos in simulink. but i want to cosimulation than it has resources issues. Please, can any one suggest any technique or method to reduce Emd.Mults and LUT's. Thanks in advance for help.
- deathblow
- Thread
- Apr 18, 2012
- Replies: 2
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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