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Recent content by deardeepa76

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    High Voltage Technology file

    Hi Erikl, Instead of specific foundries, if I want to use GPDK then which technology node would provide HV MOSFETs that can withstand 10-12V output? Can you please provide links of universities that provide technology files? Thanks, Deepa
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    High Voltage Technology file

    Hi Erikl, Thanks for the reply. Is it possible to get Cadence PDK from MOSIS free of cost for educational research purpose or should that be purchased from them? My research is not funded one, so is there any other way to get HV technology files? Who are other providers of technology files?
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    High Voltage Technology file

    Hi Erikl, Thanks for the response. My Charge Pump circuit is for pacemaker and voltage level at the maximum will be 15V. I want to use HV MOSFETs of 0.35µm BCD Technology or any of the HV technology files from TSMC, AMS etc., I am using Cadence for design and layout.
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    High Voltage Technology file

    Hi Everyone, I want to work on charge pump circuit and need HV MOSFETs for the circuit. How can I get HV Technology file, what is the procedure? Is there any open source HV Technology file available. Please give u'r inputs, Thanks, Deepa
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    [SOLVED] Simulating Semi-floating gate current mirror using HSPICE

    Hi erikl, I am graduate student and just trying to implement the mirror for my course project work. So I am in confusion whether I should follow the inputs in paper and give the results which I get as output in the project report or try to match the output in paper by changing the design...
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    [SOLVED] Simulating Semi-floating gate current mirror using HSPICE

    Hi erikl, In fig 5a on page 6, the graph showing Iin and Iout has pulses of same height (2*10-7 to -2*10-7). So my simulation output should resemble that, so only I thought keeping capacitor values as i said gives similar waveform like in paper. If i reduce the PMOS below 100fF current level is...
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    [SOLVED] Simulating Semi-floating gate current mirror using HSPICE

    Hi erikl, thanks for the response, from the 2011 paper I get these points in page 6 of the PDF: 1. For ULV inverting current mirror, the nmos transistors are minimum sized and the width of pmos evaluate transistors (MQ2 and MQ3)are increased 2. The input capacitance to NMOS CSFG transistors are...
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    [SOLVED] Simulating Semi-floating gate current mirror using HSPICE

    Hi erikl, sorry for the confusion, I am referring to my reply #19 of this thread in first page, where I have attached another base paper and this circuit I am simulating is Fig 4 (ULV inverting current mirror). Please give your inputs after checking the netlist.
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    [SOLVED] Simulating Semi-floating gate current mirror using HSPICE

    Hi erikl, thanks for the response, from the base paper I get these points in page 6 of the PDF: 1. For ULV inverting current mirror, the nmos transistors are minimum sized and the width of pmos evaluate transistors (MQ2 and MQ3)are increased 2. The input capacitance to NMOS CSFG transistors are...
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    [SOLVED] Simulating Semi-floating gate current mirror using HSPICE

    Thanks erikl, when I changed the length and width of transistors I got correct output. But I did not short the input capacitor, just kept it like what is mentioned in paper only. This is the code * ULV Inverting current mirror recharge freq 25MHz ********* Simulation Settings - General section...
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    [SOLVED] Simulating Semi-floating gate current mirror using HSPICE

    Hi erikl, waiting to know u'r inputs regarding the waveform shape. If I keep transistors in weak inversion, then I am not getting the waveform shape as shown in base paper. Anything more to be done?
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    [SOLVED] Simulating Semi-floating gate current mirror using HSPICE

    Hi erikl, I used the code you gave and the output is like this Then I tried this code, I used VDD as 450mV because I am using the same model file I posted before which has VTH0 of NMOS and PMOS equal to 450mV * ULV Inverting current mirror recharge freq 25MHz ********* Simulation Settings -...
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    [SOLVED] Simulating Semi-floating gate current mirror using HSPICE

    This is the schematic for the circuit. I have changed the typo error, but still I am not getting proper result. * ULV Inverting current mirror recharge freq 25MHz ********* Simulation Settings - General section ********* .include "D:\HSPICE\NewCSFGBkup\t96w_9sf_9m_lb_3-params.txt" .param...
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    [SOLVED] Simulating Semi-floating gate current mirror using HSPICE

    Hi erikl, I have another mirror circuit Fig 4,from this paper This is the code is used for simulation * ULV Inverting current mirror recharge freq 25MHz ********* Simulation Settings - General section ********* .include "D:\HSPICE\NewCSFGBkup\t96w_9sf_9m_lb_3-params.txt" .param vdd=450m...
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    [SOLVED] Simulating Semi-floating gate current mirror using HSPICE

    :grin:Finally I got it, thanks a lot erikl, your inputs was of utmost help to me. Thanks for taking u'r time and effort to help me out:grin: * CSFG Common gate current mirror recharge freq 100MHz ********* Simulation Settings - General section ********* .include...
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