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why do you want to use glitch as real asynchronous reset to FF, think of this and may be you should start calling it with a different name if it was intentional
To simplify things lets look at the below example :
you are havinig a active-high reset to a FF which means when ever reset is HIGH, you will reset the Flop.
Now you have introduced a AND gate i.e. RESET_NEW = RESET & CONTROL
Intention is that we want to have RESET = 1 and CONTROL = 1 then...
For the two scenarios mentioned as "a" and "b", data will be lost.
If we chose a FIFO of certain depth, and if we dont know how the reciever is gonna take the data out from the FIFO, FIFO will be full after a period of time since you are continously sending new daya every clock cycle.
Quick things to look at apart from what "chids" has mentioned:
1. Look out for High Fan-out nets
2. Look at the levels of logic created by the synthesis tool, correlate that with your RTL code and see if you re-write in a better way so that tool can implement it in a better way
3. Look at the...
Hi All,
if we have an o/p port where it will be connected to the Data-pin of Latch, We need to use -level_sensitive option when defining output delay constraint.
Would like to know if some body has used the above option and can give me an example of the timing report with and without this...
Re: ERROR:Pack:2310 - Too many comps of type "BUFG" found to fit this device
Incase if you think that you dont have timing critical path and the generated clocks dont have too much of load, there is way where u can specifiy to the tool not to insert any buffer on a particular signal...
Generate a clock from PLL of 80MHZ from your input clock(40 MHZ), The newly generated clock will have 12.5ns clock period and that matches your delay requirement.
This is one of the method, if it is a smaller delay, would have gone with buffer insertion.
I have modified the code, added reset and default value for state_next and LEDs_next to avoid latch inference.
Just add this piece of code in to your module, shouldnt get any warnings.
if you look at your state machine, its always in "idle state". Is that Intended?
Look at your state machine code, there is a chance for latches as you have not completely used your states and more over timer done signal is not used.
re-check your code before you think of anything else.
Here are some tips which might help in improving the timing :
1. Flattening of the design
2. Register Duplication
3. FSM state encoding (Can be changed in Xilinx Synthesis tool)
4. Register Balancing
Expect that synthesis tool might do optimization for the below code :
assign mem_full = (addr > 63) ? 1 : 0;
But the above can be rewritten as :
assign mem_full = addr[6];
If "addr" is 64 and beyond, it will be 1. It can 64 and beyond if and only addr[6] is 1.
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