Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
#1. SCAN Chain is a Serail Shift register structure...where in you can pump in/out data from Chip pins, and with scan_enable control you can bring the data into FLOP from D path instaed for SI path, i.e. known as Capture cycle
#2. Compression s is nothing but comressing the data pumped into/out...
Actually a hold causes the data shift out a cycle faster, so expected data comes a cycle early, so bypass the hold-violated flop from the chain, by hacking the netlist and regenerate the patterns also you have to mask the capture data coming to the hold-violating flop.
Here we definitely loose...
Hi,
Let me answer, By modifying the netlist for failing flop we can re-generate the patterns and validate the silicon , this is one method.
So like this I wanted to know is their any other method/soltions present to test the silicon.
Ok.. let me repeat....
Issue is present on Silicon and I have identified the flop with hold violation (not a metastability), so the expected data is coming one cycle ahead..
Then what would be the solution w.r.t. atpg.
lostinxlation,
Exactly you are correct for the violation falling in hold window,
I am also expecting for the other scenario
i.e. if the hold value changes before the setup, so no metastability is present.
__ | __
__| |__| |__
:?: :-x
What is the solution? Please recheck the question once again.
This is a discussion topic. We can discuss all the available solutions for hold-issue on silicon.
Ravi,
In your case you have to have a separate configuration saying you are in stuck at mode or in transition(TFT) mode,
So in tft mode the chain lengths will be lesser because you have to bypass the clock logic. By this way you can get the stuck at coverage on 'clock logic' but you can have...
ASIC-DFT Hold Violation in Tester and regeneration of ATPG with hold mask
Hi ,
Can any body discuss about the procedures to generate the patterns, for silicon-hold violation issue -seen on a chain/flop.
In Brief:
On silicon I am seeing a hold violation on a chain and have identified the...
xor gate from two mux
Hi,
You can design any logic using mux in two ways,using Levevls and/or using interconnection between differernt nodes.
For XOR implementation..interconnection without using Levels
(A)i0------!\
! !__Y
i1 !---! !
! !/
!__ ...
Hi,
for FSM coding using HDL,refer HDL Chip Design by Douglas J. Smith.
You can code a FSM in 3 different ways.
Go through this book you will deffinitely find a good solution for FSM coding.
This book is a very good HDL coding qudelines for every one.
Thanks
Shailesh
Hi,
I want to generate the vectors(atpg),for that which TDL is the best suited and why.
Tell me the advantage and diadvantage of each TDL:
TDLs like WGL,STIL and VERILOG
Thanks & regards
SHailesh
mod function
In this data sync.. issue will deffinitely come into picture,because you wanted to design a Combo design.Make all the division to occur parallely.
You have to go for parallel computing algorithms.
Many algorithms are there,for example to speed up the multiplication you can use...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
