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You can do everything in verilog! Everything! But you could check out myhdl, which should be able to do what you want. Myhdl generates a verilog file which you could use to learn how to do this in verilog. Also, check out migen.
Johannes
Hi,
did you bypass the supply of the OPAs? I remember some weird behavior by an OPAmp because I forgot to bypass the voltage on both supply rails. I think I solved the issues by putting in two tantalums with 10uF.
Can we see the layout?
Johannes
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