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Need a tone generator
I want to build a tone generator to inject busy tone or dial tone into PCM channel. How can I produce such 64K signal of busy tone or dial tone?
Any help is appreciated.
tcp programming
I use TCP socket to send data over Ethernet. I get packets jointed in received port. I need to separate them in application program. Suppose TCP should not work like this. Any settings I missed? Please help me. Thanks.
Not every 2.048M clock is ok. Predator wants to get a 2.048M clock synchronous to 19.44M. That's the problem. The 63 E1s demux from STM1 are not synchronous to the STM-1 carrier either.
Two possible reasons:
1. multiple definitions on variable "OSMapTbl"
2. recursively including header file in other header files. You can prevent from such case by using "#ifndef xxxx" to enclose the whole header file. For example:
#ifndef __header_file_name__
#define...
Clock recovery circuit will extract clock signal from received data. It is generally used in synchronous communication system. Data does not always have transition on each clock edge so it's not easy to derive clock from the data stream. PLL or SAW is used to do this. The extracted clock is...
Hi,
Do you know any tiny RAMDISK and file system can be ported to embedded system. There is no disk on my target board. I need to build file system in RAM. Any open source code available?
Hi Maestor,
Jitter is measured as the position offset comparing to an ideal clock edge. To make a PLL design meet the jitter spec., you need to distribute each adjustment opportunity as uniformly as possible and minimize each adjustment offset at the same time.
Hi Predator,
You can design a digital PLL in FPGA with 8K reference input as well as a 32.768M master clock. The 8K clock can be derived from overhead signal. If you want to meet the jitter requirement of ITU-T, you need to double the master clock and then use both edges to lock to the reference.
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