Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: testbench simulation
First you create the test bench in the same proyect where you VHDL document are.
Second, You need to visualise the code to test as a black box, you need to know all the inputs and outputs.
Finally you create the stimulus signals for the inputs and you will have the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
