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when i use DC to synthesize a top module :
module TOP(I2C_01H[1],I2C_01H[3],I2C_01H[2],...);
...
endmodule
after synthesis : the module become :
module TOP(Port1,Port2,Port3,...);
...
endmodule
DC has changed the top port_names ! I want to preserve the former port_name after synthesis .so...
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