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Recent content by dasong

  1. D

    Help me understand calculating poles for op-amp

    Op-Amp i think you will get the answer fater you read the chapter 10 of Raviva's book
  2. D

    Which technology is preferable in RF and memory design?

    layout design i heard IBM' process was good
  3. D

    Tips for VCO layout at 1M frequency

    VCO layout i think you should take care the match of the inverter chain
  4. D

    Question about PCell from Tools menu

    you can directly instance it from the lib
  5. D

    Output stage of CMOS Image Sensor's amplifier

    ambreesh ,can you tell me the most performance difference between 4T pixel and 3T pixel,thanks!
  6. D

    Why "reset" in image sensor pixel?

    TO cancel the FPN noise in photodiode
  7. D

    CMOS Image Sensor and FIFO ground

    I am a newman for cmos sensors design ,who can gave me some useful message for it,thanks
  8. D

    How do I start to design this bandgap circuit?

    I have the same question during the bandgap design
  9. D

    6T SRAM transistor sizing

    sram transistor ratio you can see the book Analysis and design of degital integrated circuit design,it has indouction how calculate to the w/l radio
  10. D

    Help(Cadence IC5.0 Setup)!!!

    setup IC5.0 is very complex,you can setup IC5141
  11. D

    CMOS opamp spice net list

    nmos pspice netlist you can use the two stage cascode opa
  12. D

    Why is polysilicon used instead of metal for gates in MOS?

    Re: Basic MOS question with the develop of process ,maybe use matal gate in the futher
  13. D

    Noise analysis of PLL using HSPICE

    i have analysis the PLL's noise use Spetrice,someone tell me analysis the PLL's noise need the noise modol.
  14. D

    The design of low speed high resolution DAC

    i had designed a sigma-delta ADC,if your DAC use sigma-delta?
  15. D

    Looking for the circuit of electroencephalogram (EEG)

    Re: Help you can use google of advance research.
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