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Re: How to make an integrator with vcvs(ideal opamp)
Thank you for your answer.What's the reset switch,
Is this instance?where should i put it in.
OR how to add an initial condition,in the analog enviroment or the vsource? Thanks.
How to make an integrator with vcvs(ideal opamp)
I made an ideal opamp with vcvs.But when i used this op to make an integrator sth just went wrong.Any dc voltage of input will make the output become VMAX or VMIN.Can anyone tell me why and how to solve this problem?
Thank you very much.
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What should i do to make this ideal opamp work.Should i use the “Model Editor"of cadence to create some file and put it in the veriloga folder?Thank you for you reply.
Dear dick_freebird
I copied the software from the lab of my school.There is no ahdlLib.I download this one from another Thread:
https://www.edaboard.com/showthread.php?309184-can-anyone-send-me-ahdlLib-library
Also i tried to find the library from the website of Cadence but the website just give...
Dear frankrose
Yes,you are right.There is only a symbol view.Is it the problem of the library?Or i should do some work before i use it.Thank you for your help.
I get the ahdlLib from another thread and edit the cds.lib to import this library.But when it got to simulation(i only used the "opamp" in ahdllib and some vdc gnd etc..) i got an error below:
Can anyone tell me why and how to solve this?Thank you very much.
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