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thanks, My solutions was going to be to make more integers called: thousands, hundreds, tens and ones, and the dec's inside the process will be changed to their respective integers.
signal dec, z, thousands, hundreds, tens, ones : integer;
seg_2_loop : process(dec)
I have the error in my VHDL design project:
So I know that it has something to do with that there are two instances that are driving this decimal signal but I am confused as I thought I only have one instance driving it, I'd appreciate it if someone can spot the point of the error and fill me...