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I would like to ask your opinion regarding NMOS test-bench as a varactor (voltage control capacitor). I am trying to find the properties of Vg,W for achieving a 200[fF] capacitor.
Here is my test-bench :
Calculated C using AC analysis, where - C = I/(V*2*pi*f), I = NMOS-Gate point and V =...
I just found this in the PDK -
>>>>spice model notice<<<<
The current version of spice model still doesn't support Monte Carlo simulation.
The Monte Carlo model will be support in the feature.
:/
Hi all,
After reading some threats in the forum, I couldn't find an answer to my question - I am using a TSMC 130nm RF spice model and trying to simulate mismatch in Cadence ADXL with MonteCarlo analysis, with no luck.
I was able to simulate corners with no problem (SS,FF,TT,SF,FS) but when...
Yes this is correct as it is exactly correspond to the dynamic range definition. But in order to be accurate on low signals, your signal power should be 15 dB more than the noise level (e.g -95 dBm) to not suffer from over-gain losses.
Also, while looking at high power signals, be aware of the...
Thanks for the explanation, I understand the input pole now - Cgg is the total input capacitance.
for the output pole without Cout load, which capacitance should I take into consideration ? I have taken Cgd*MILLER_AMP (which equal 1.8) and Cdb and got an output pole of 112G instead of 66G...
I would like to compare my pole simulation results to my hand calculations, I'm receiving quite a big error. when simulating a Common Source stage without output capacitance load there is a big difference between the simulated and the calculated poles, when I'm adding a capacitor load the output...
regarding -
what do you mean by sitting on the positive rail ? if V2 will increase the voltage (V_ref) through R3 will try to decrease V2 and not increase it. please explain.
R1 determine the nodes current and I have calculated it is sufficient enough (I=Vt*ln(N)\R1 where N- number of diodes...
Hi all, I'm having troubles designing this circuit which supposed to be a BandGap circuit with op-amp topology (instead of current mirrors).
in theory, the op-amp supposed to force V2=Vd using a negative feedback. in simulation you can see that Vd is not equal to V2 (~70mV difference) and if I...
Self biased is the term (Razavi also called it that way) and it comes because the transistor biased itself with “no help” from outside source...
Can you elaborate please regarding the AC behavior ? Does the small/large signal behavior will change? Rout?
HI,
I would like to know what's the difference between the two circuits act as a Bias circuit ? one is "self-biased" and the other is diode connected device.
as you can see from simulation, they both Bias the transistor at the same operating point and both has same model parameters (gds,ron...)...
thank you again vive for the answer, but maybe I will make myself more clear - I am in a more beginner stage right now. I cannot seem to calculate the right Bias voltage (e.g Vg) for each transistor in order for it to be in saturation and receive high gain (high Rout from M2,M0,M3). it seems...
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