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tri-state buffer
why have the tri-state buffer based buses higher delay comparing to non tri-state buffer? why is the mux based bus more commonly used?
As I check standard cell library, there isn't too much delay gap between tri-state buffer and non tri-state buffer?
io ring basic
you mean power ring?
when you do P & R, we place power ring.
There are two power ring.
One is for I/O pad, and we call that IO ring.
The other is for core cell, and we also call that core ring.
Gob bless you!
clock buffer vs normal buffer
When we use clock buffer, its purpose is to equal duty cycle for all f/f.
whereas, when we use normal buffer, its purpose is to meet timing.
The timescale of normal buffer is smaller than clock buffer.
Normal buffer is related with set-up/hole timing violation...
I found the reason why # delay does not work.
If we use # delay, we states time like # 1, # 30 and etc.
But unless we did not describe timescale, ncverilog cannot decide how many times it delay. So we must describe like as below.
`timescale 1ns/10ps or other unit
Anyway, thank you for your...
While I simulate my design, I meet some trouble.
In my RTL code(verilog), there is # delay statement like as below.
assign #1 DMAReady = iDMAReady;
At wave viewer, DMAReady signal has unknown value.
Did you have experience about that, friends?
Does it related tool's option?
FYI,
I'm using...
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