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Hi,
I wanted to insert cell using script in innovus during eco.
I intended to using ecoAddrepeater command for this, and wanted to add prefix for the cell added. (e.g. eco_fix_leak )
is there any way to add prefix to inst ?
Really looking forward to your reply!
Hi guys,
I am confused that why we do CTS in physical design?
The obvious purpose for CTS is to reduce CLK skew, and then fix timing violation(mainly setup). And I realized that for low-speed device, timing is easy to meet. So I wonder why we still need CTS in low speed device design.
Here are...
DC uses WLM for timing opt, and DC topology will create a virtual floorplan and uses it for opt. And the floorplan info created during DCT is stored in ddc. Did I make mistakes in understanding this ? :)
Hi,
I used the ddc file from DCT, and executed floorplan and placement. Timing slack after DCT is tolerable(0.6), while after placement is 8.2.
Here are what i did.
1. created_fp_placement -effort high
2. place_opt -spg -optimize_dft -area_recovery -power
3. run" incremental opt"
And here...
Hi,
Do we need to set timing constraints at each stage during physical design (from DC compiler to signoff)
If so, how to set timing constraints during placement? (Also source sdc file?)
Looking forward to your kind help, friends!
Hi,
I learned there are 2 ways to read designs when we do floorplan.
1. read_verilog...
2.import_designs ... ddc ..
I wonder (1)What's the difference between these two ways?
(2) initial floor plan info generated from DCT is contained in ddc, is it also contained in verilog?
So many thanks!
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