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@dick_freebird : I am trying to simulate a 3 stage common source amplifier to make a ring oscillator. I have given Vdd and ran the simulation for transient analysis. I do not see any oscillation. I am seeing only the dc voltage at the output of each stage. Can you tell me where i am going...
Also i want to know if we can plot Ron in deep triode for Vgs sweep. How should the graph look like and also how to do this.
This is how i am trying, please let me know if it is right. I am doing a dc analysis on nmos first. then i am trying to do parametric analysis on Vgs keeping Vdd constant...
Thank you all for your replies. It was useful in trying to understand the concept.
Varunkant : can you explain how to make ron as a output variable in cadence?
Hey,
I am trying to work on SRAM cell in cadence. Could any1 help with with the simulation of the butterfly curve in cadence? please help me out.
Thank you
Mohana
Hiii
I am trying to design a LC-VCO with WLAN as its application.
I would like to know what should be the frequency range for WLAN. from the ieee standard wlan has frequency of 2.4, 3.6 and 5GHz. which one should be choosen and y???
I would also like to know about the offset that should be...
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