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Recent content by daffo123

  1. D

    how to do a scan chain in Astro?

    Hi chyau Please let us know the detail reordering flow if you possible. thanks, daffo
  2. D

    Use Clock Rising and falling edge when running synthesis

    Thank you very much all of responders. It is very very helpful for me Best Regards.
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    Use Clock Rising and falling edge when running synthesis

    Dear All. Is there any idea to use both clock rising and falling edge when we run synthesis? I got an error message when I use both the rising and falling edge in synthesis. Please let me know if you have ideas or experiences. Thank you.
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    Occured Errors while running elaboration in Synthesis

    Dear ALL. I got some errors running elaboration after analyze with my code below in Synthesis The error message as follows Error: /work/ddr_ctrl.v:74: Clock expression must be one bit wide. (ELAB-367) Error: /work/ddr_ctrl.v:74: Clock expression must be one bit wide. (ELAB-367) Error...
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    Question of import gds from encounter using Virtuoso.

    I want to run the drc/lvs with calibre on Virtuoso. My gds made from a DEF of SoC encounter. I find that a lot of cells are overlapped, when I run import a gds from the encounter. In fact, a GDS on Encounter has no problem, I mean, not overlapped. but exporting gds from encounter and then...
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    what should be power ring width for 6000umx6000um chip ?

    power ring width....... I want to know an appropriate power ring width for 6000umx6000um chip size of 90n process. Please let me know. Thanks in advance.
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    What are the differences between SDF versus SPEF?

    SDF versus SPEF I forgot the differences between SDF and SPEF. Pls.... Someone tells me the difference. According to my old memories... SDF has only cell delay and spef has RC interconnection delay... I want to know.... Please let me know the truth. Thanks in advance.
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    TSMC018um Design rule....

    Hello... Can you tell me the minimum space between io pad and io pad in TSMC018um? Also please let me know the min. space between bond pad and bond pad? Thanks in advance
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    Qustions of a staggered and a inline io

    I 'm going to use tpz973gv digital io by TSMC which is staggered io. I have 2 questions. 1. Is it possible to use inline analog io by tsmc and tpz973gv together? 2. Do I use the tpz973gv for not staggered io but inline io ?? Please let me konw... Thanks in advance.
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    hspice netlist extraction

    Dear All. I want to extract a spice netlist on virtuoso schmatic, but there is no hspiceD or hspiceS view in my lib. In this case, How can I extract spice netlist? Please help if someone has same experience.... Thanks in advance
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    TSMC lib what arethe differences between FE,FB and FX?

    Question of TSMC lib I want to know the differences between FE,FB and FX. Please let me know if anybody knows them. Thanks in advance.
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    up to 400MHz FIFO Memory -request for resources

    up to 400MHz FIFO Memory Dear all. Do you have any datasheet or know a website supporting up to 400MHz FIFO Memory. Please let me know if you have or know. thanks in advance
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    Need IO and pad open size of TSMC018um

    Re: IO PAD Size... You got it. I have no gds.
  14. D

    Need IO and pad open size of TSMC018um

    Re: IO PAD Size... Thank you.. I think, 65um x 65um is a pad open(bond-pad) size. Please let me know std IO size of 0.18um .
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    Need IO and pad open size of TSMC018um

    Dear All I want to know IO and pad open size of TSMC018um. Please let me know the width and length of them... Thanks in advance
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