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Recent content by dada999

  1. D

    Critical path has changed after I have changed timing constraints...Why?

    Thanks very much. I also found that the area is much larger when the clock is set very tight, is this normal during synthesis?
  2. D

    Critical path has changed after I have changed timing constraints...Why?

    Thanks for your reply! I think I have understood the result. Another question is, after I have synthesized my design, can synopsys dc tell me how much power it will consume under the clock frequency of 50MHz? I dont need the data by using report power since this power is under the extreme tight...
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    Critical path has changed after I have changed timing constraints...Why?

    Dear all, Thanks in advance for your help! I have synthesized my design in synopsys design vision, at first I create the clock to 10 ns, and the timing report showed that slack is 0, and the critical path is one bigger multiplier. Then I changed the clock to 4ns, this time it took me more...
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