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Re: LVS error: psub-stampErrorMult" "psub-StampErrorConnect" "Wel-StampErrorMult"
In my opinon, i think you can read the lvs commad file first to check the error's reason.
if you want to read it, you should use erc check for it or check soft-connect.
but i suggest you read the command file...
i suggest you read the manual, and you can get much information for the tool.
while i use this tool, i read it and then use it for layout.
Do the layout is easy, but you should know about simiconduct knowledge and device structure.
That is my opinion
Re: calibre pex manual
if you run lpe for rcc, you should include the r and c ext model.
suggest you do the cc fist, find the error.
please take care ground node. if you will use ldd devices, please check the subcirt for ldd
The layout created by macro is flatten.
If you just layout the diff input pair, i think you can insert mos/bjt cell that will more usefull.
And you can create a tcell with parameter what you want, it will easy and usefull.
---------- Post added at 02:40 AM ---------- Previous post was at 02:35...
Re: OSC layout question
yes. The circuit is a cascade style.
Now, i do not know the osc function and how to oscilation. Do you some paper or book about it?
My work is layout not circuit.
Thanks
Re: Mosfet Mismatch
In my opinion
first, you can use symmetry structure which you can find in many books.
second, you can refer to the foundry which you can get their PCM or electronics parameter, and maybe here are some discreption about mismatch parameter. You can calculate the MOS by the...
3 terminal resistor?
You should read the doc from foundry. Here are some descriptions about it.
Usually, we think if pwell,connect gnd; if nwell connect vdd. But if you want to get less noise, you should connect the third terminal to gnd.
here the well should an signal well which sourronding...
First, you should using verification tool diva, dracula or calibre get the extracted file, and annoded the parisitic parameter. I know the cadence cdsdoc include some paper refer to it. you can read it
DAC layout
I think you should ask your circuit designer and know the circuit's architeture. Then you know how to place the function module. Maybe some infor you can get from your parter.
The finger transistors can use the S/D node.
And the multipliers are signle transistors with themsleve's S/D.
You should layout the finger transisitor and multipliers,and you will know all.
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