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100Hz 20mV p-p noise
circuit: a low noise preamplifer and two stage active RC filters.
bare chip, chip-on-board bonding to a small PCB
the chip bonded PCB is mounted onto a test PCB
20uF//0.01uF bypass capacitors placed close to the power connector @ test PCB
1uF cap placed close to each VDD...
Re: for ac simulation
Yes, it is from the <analog integrated circuit design> by david johns and Ken Martin. Just making some changes on transistor dimensions. I tried it before using on-chip resistor. No oscillation. So never thought it could be a pro.
For the stray cap, I poured grn around...
the first-order means linear approx. literally. But it is a little bit misleading in our case. My understanding is that first-order means major effect. e.g. gm is a first-order parameter while ro is not.
implantation is a IC process, you can find in lots of textbook. It can implant donnor or...
Thanks, Tsanlee,
I fogot to show the startup circuit in the schem. The bias circuit has two stable points: Ib=0, and Ib=f(Rb). From the simulation, it looks like if parasitical cap is over ~1pF, the bias circuit tends to stablized @ Ib=0, which activate the startup circuit. And then it goes in...
explain bais
Help!
I used a bias circuit as below, and found some oscillation. Rb is off-chip, so I can see Vb-voltage drop on Rb oscillating between 0 and some value. The oscillation frequency is related to stray capacitance at the pin connecting Rb. And this oscillation can be seen in HSPICE...
Re: Transconductance of input stage in folded cascoded opamp
parasitic gate resistance shoule be considered for very large w input transistor, using multi-slice layout and connecting both end may reduce it.
And for very large w/l and low drain current, transistor may work at weak inversion...
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