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That sounds reasonable, although I don't find any this assumption Dr. Razavi made in the book.
Anyone has the idea on the values or ranges of r0 and RD in practice?
The following attached file is a noise analysis example in Razavi's book "Design of analog cmos ICs" at page218-219.
I think, in Eq(7.38 ) , the last term RD^2 should be (RD||r0)^2, where r0 is the output resistance of M1.
Is it right?
Hi flatulent,
I was also told that the carrier frequency must be greater than half the bandwidth, to avoid having the spectrum wrap around 0Hz.
Is it right?
How to understand "avoid having the spectrum wrap around 0Hz" or in your words "As long as the spectrum does not go down past zero...
I have to design a mixer-signal QPSK demodulator for a wireless data link targetting max data rate.
I am just wondering what the limit for the data rate of QPSK is. Is it possible to achieve 5Mbps data rate on 13.5MHz carrier frequency with reasonable BER?
Analog_design did catch my meaning.
Since there are many experienced analog guys in this forum, I'd like to know their design methodologies. For example, if you are assigned to design a bandgap, or LDO, or ADC, how do you plan, start, and finish it in good quality?
You can find the model file named "mm018.scs" in Cadence directory. It includes all spectre models you want. For example,
1.8V P+/NW/PSUB 10x10, 5x5 and 2x2 vertical PNP bipolar and N+/PW/DNW 10x10, 5x5 and 2x2 vertical NPN bipolar
or
3.3V P+/NW/PSUB 10x10, 5x5 and 2x2 vertical PNP bipolar...
Re: How to analyze two analog IC blocks( Pls see attached fi
Hi electronrancher,
Intuitively, I think your analysis is right. However, I could not derive your
formula Iout = Iin(1+(R2/R1). In my equation, the Iout/Iin ratio always depends on gm.
Could you give a further explanation on how to...
Hi electronrancher,
Thanks for your great analysis. I cannot agree with you more on this circuit.
Could you give a further explanation on the another circuit that I post in the forum Analog IC Design & Layout?
Thanks for your reply.
I got the circuit diagram just like this. However, we may suppose the output node is the M5's gate/source. So, it looks like a current source. And I think the key is the resistor R1...
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