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Recent content by cyteng

  1. C

    Symbol recovery using correlation

    You need to do timing synchronization to find the exact sampling point.
  2. C

    How and where can I master to use Modelsim6?

    Reading the manual thoroughly is the best way to learn Modelsim if you got time.
  3. C

    How to decrease time slacks in Synplify Pro?

    Re: Synplify Pro timing I found overset the clock frequency can get better results.
  4. C

    who ever did pwm chip with fpga

    Sorry , blank was omitted so my drawing doesn't make sense. If you interpolate 16 levels in one PWM time and assume the current signal amplitude is 0.5 , the timer or counter result will like : 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0, the adder result will like : 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1...
  5. C

    The difference between PCI , cardbus and mini PCI.

    PCI and cardbus Who can tell me the differences among PCI , cardbus and mini PCI. Thanks !
  6. C

    who ever did pwm chip with fpga

    Sorry , the previous one's position is shifted, So I redraw it. __________ | | |__________, if adder , you will get ___ ___ | | | | | | | | | | | | ____| |___| |____...
  7. C

    who ever did pwm chip with fpga

    If you use timer or counter , the pulse is like __________ | |...
  8. C

    who ever did pwm chip with fpga

    You can use an adder to implement PWM function and the carry of msb will be the final output.
  9. C

    Ifft for dvb-t - looking for an algorithm

    You can use radix-4 structure. opencores has a free ip about it.
  10. C

    Looking for standards and source codes for JPEG project

    JPEG project I want to do jpeg and motion jpeg project. Where can I find the related standard and reference C source code ? Cyteng
  11. C

    ease to design a common fifo (syn/asyn), not high speed

    How fast do you consider it as "high speed" ?
  12. C

    fpga to asic convertion--help

    The answer is very simple. Design a separate power on reset circuit on the ASIC. And when the power is stable , write the initial values to the RAM. cyteng
  13. C

    Which is the best commercial verilog simulator?

    Verilog-XL
  14. C

    A synthesis problem about Design Compiler

    design compiler synthesis If I would like to change the net name *cell*11/U2/CONTROL1 to NCONTROL1 , how do I write define_name_rulse command ? I use "define_name_rules myrule -map {{"\*cell\*","U"}}", but it maps "*cell*11/U2/CONTROL1" to "U".
  15. C

    A synthesis problem about Design Compiler

    design compiler naming rule After synthesis and optimization of my verilog file, I find some net( or wire) names is very strange. For example , the net connected from the output of nor gate to the data input of D flip-flop is called " *cell*11/U2/control ". But I want very short net name like "...
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