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Recent content by Cyrk

  1. C

    High speed charge pumps

    I dont need higher CP gain, i need faster switching. Right now my CP output is not even close to rectangular inpulses matching PFD output. I need some kind of article or book with detailed explanation of CP various topologies. Or at the very least a 1-20GHz CP schematic. Thx for help in advance...
  2. C

    High speed charge pumps

    Hi. I'm looking for some info about CMOS high speed charge pumps (schematics, layout issues ect.). The design i'm curently using is not fast enough. Thx for any help
  3. C

    Reference current source in CMOS

    Thank you. This is exactly what I was looking for.
  4. C

    Reference current source in CMOS

    Hi. As you can read in the topic i'm looking for a schematic or something like that for reference current source. But the trick is i cannot use bipolar transistors - only mos transistors and resistors. Source should give stable current value in widest possible supply voltage range. Thank you...
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    What is the best architecture for VCO with the tuning range from 600 MHz to 1.2 GHz?

    Re: VCO tuning range Hi. The main difference between LC tank based VCO and inverter chain ring VCO is that with the first one you'll get ALOT cleaner output (as mentioned above phase noise performance will be better by far) but it will be harder to achive 600 - 1200 MHz tuning range. On the...
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    what is wrong with my PLL loop filter voltage?

    Hi. That realy depends. There's always a trade off: locking time vs. Δf (in your case Δf is 40-50kHz). You can redesign your loop filter (decrease loop bandwidth) which will result in ripple decrease, but at the same time it will increase locking time. If you have a specification for your pll...
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    ERROR-Convergence problem in bias point calculation (PSpice)

    convergence problem in bias point calculation Hi. I have yet another problem with Pspice Any idea what can cause this and how to avoid it?
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    Enclosed oscillator simulations problems in PSpice 9.1

    Spice simulations It worked! Thank you very much - you're a life saver
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    Enclosed oscillator simulations problems in PSpice 9.1

    Re: Spice simulations Actualy I'm not getting any errors, just a flat line instead of oscilations at output. VDD VDD 0 DC 1.22V isn't the first line. I've put large resistors, remover shorted capacitor but I'm still geting flatline. Plot from winspice: **broken link removed** and a plot from...
  10. C

    How to make NMOS transistor more rectangular in layout?

    Large NMOS Hi. Is there any way to make NMOS transistor (l=200u w=5u) more rectangular in layout?
  11. C

    Enclosed oscillator simulations problems in PSpice 9.1

    Hi. I'm having trouble simulating enclosed oscilator (3-stage crappy design) with PSpice 9.1 (it works just fine on WinSpice and HSpice). Any idea why? Thank you in advance ******************************** VDD VDD 0 DC 1.22V VGND GND 0 DC 0V M1000 N1 OUT VDD Vdd pfet w=16.2u l=5.2u +...
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