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Hi All,
I am looking for adding delay buf at hold endpoints ,trying to trace out common point,so that i can put a buf at that point to see changes across all violating endpoints,I am stuck at the point ,to get the common point for example 1000 unique endpoints,please share your thoughts on how...
Hi,
I am seeing some double switching violations.
Please guide me, wht r those vioaltons and how to fix them.
and what r other checks we have to do other than setup and hold.
Hi
I hace cadence .lib format and rtl compiler how to ocnvert them to .db ?? i want to use it in dc compiler,but i dont have library compiler option.Please help.
Hi,
I am using ic compiler an during read verilog i am getting an issue.
the error report is
import_designs -format verilog -top ChipTop -cel ChipTop {../../dc/output/compile.v}
Warning: /home/training/my_pnr/icc/ref/SAED32_2012-12-25/lib/stdcell_rvt/milkyway/saed32nm_rvt_1p9m: bus naming...
Hi
I have synthesized a rtl using lvt and hvt cells.I dumped out netlist and when taking in to pnr tool ,i got errors saying the hvt cells are marked dont use.
so my physical data is not coming.i am unable to change the attribute also,again it is saying they are dont use cells.
remove...
no memories no apds,just rtl only.i read all and i have tried still there are errors.
what i have observed is 8 unsolved references.
there are 2 rtl files not read,later i read in to the memory.Now if i do they are linking.But if i change the current esign to top,again same 8 unresolved...
Hi
I am running a hierarchical design in dc shell. I loaded design and libs sdc. Now when i do link it is saying 9 unsolved references.What should i do to fix this??
When i do Compile _ultra it exits shell with command code 0; only compile command is working fine. Please clarify.
I did tkdiff between old lef which is supporting and new leaf which i am using.
Even though Syntaxes are same it is showing parse problem.
The defined variables are in same order.
It was not defined like that. Even i tried interchanging those two lines, but it is showing this error.
Some times tool is stopping at other points. When it is fine in innovus but why not in encounter??
Hi all,
I am loading a design in innovus by following commands and it is working fine
source xyz.globals
init_design
but when i do it in older version of encounter while readding tech lef the below error messages are coming.i need a fix to this problem,
Loading LEF file pqrs.lef...
ERROR...
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