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Re: AMBA AHB Master
Next step is to create a Micro-architecture doc/spec. Some leads/pointers:
1. Are you designing Master or Slave or both? If it is for student project I recommend you do Slave RTL with master Testbench to keep it simple/started.
2. What testbnech language?
3. What tools do...
Your CV does look good - if you can really demonstrate that you have done the full coding for CAN/APB etc. including "synthesizable testbench" on a face-to-face interview @CVC (CVC Pvt.Ltd., - Home) we would like to consider your candidature. Apply with confidence to career@cvcblr.com.
We...
You need to link appropriate PLI SO files to VSIM. Usually the SNPS Power compiler should provide this for you - I believe you use that to generate the SAIF file.
Look at:
$SYNOPSYS/auxx/syn/power/vpower/lib-$ARCH/libvpower.so
Note that $SYNOPSYS variable should be set to your SYNOPSYS...
Re: low power ASIC RTL
Basically you need to be writing UPF/CPF files and mention your PDs. The tweak your stimulus to model the Power State Table. You may also add assertions to verify the Power Management Unit (PMU) and func-cov to ensure full testing.
During previous academic year, Sugnath...
Re: VCS error message
Show us how you invoke VCS. My guess is you had "file.sv" as
module m;
endmodule : m
And then you passed to VCS (wrongly) with -f arg as:
vcs -f file.sv
If the above guess is right, remove the -f, it should work. Else show us your exact command for more help...
You are using "Cross Module access" which is called XMR - it is not allowed in Synthesis. You need to write to SRAM via addr/data interface/pins.
Regards
TeamCVC
www.cvcblr.com/blog
Hi,
Any such INTERNAL Error is a bug in tool, report to support center. Also you may want to try latest version (9.2?). On your code you are missing a return data type specification in function declaration as:
>> function flush_cmd_queues();
function void flush_cmd_queues();
Maybe that...
Re: counters
What is the "problem"? Compile error? Simulation issue?
That looks like your requirement - where is your attempt to solve it?
TeamCVC
www.cvcblr.com/blog
`define is pre-processor directive, hence gets expanded before the elab stage - i.e. when the generates are handled.
If you explain your requirements, maybe we can help out with better code. Perhaps you need a simple variable set by generate during elab stage?
Regards
TeamCVC
www.cvcblr.com/blog
It looks like there was no activity on your signals hence the VCD file is empty of "value changes". Did you see a waveform in Modelsim? If so do you have a vsim.wlf file created? If yes you may also use
wlf2vcd (or something similar)
to create VCD out of WLF file.
Regards
TeamCVC...
If you are good at SystemVerilog with OVM (www.ovmworld.org) and can develop TLM tests, send your CV immediately to career@cvcblr.com
Regards
TeamCVC
www.cvcblr.com/blog
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