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i fixed the problem with dual-port RAM:
entity RAM is
port ( clka: in std_logic;
wea: in std_logic;
a: in std_logic_vector(7 downto 0);
dia: in std_logic_vector(15 downto 0);
doa: out std_logic_vector(15 downto 0);
clkb: in std_logic;
web: in std_logic;
b: in std_logic_vector(7 downto 0);
dib...
What`s the problem, i have RAM overlap... On signal doout2 i have nothing... I used Single-Port RAM with Asynchonous Read... This is my code:
entity TryCode is
Port ( clk : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR (7 downto 0);
dina : in STD_LOGIC_VECTOR (15 downto...
I try this logic too, but i am not sure that it is the right one:
entity Three_st is
port( T: in std_logic;
I: in std_logic_vector(15 downto 0);
O: out std_logic);
end Three_st;
architecture Behav5 of Three_st is
begin
process(I,T)
begin
if (T = '1') then
if (I = "0000010000000000") then
O <=...
I am sorry, but my English is not perfect :roll:
I want to realize this logic:
entity Three_st is
port( T: in std_logic;
I: in std_logic_vector(15 downto 0);
O: out std_logic);
end Three_st;
architecture Behav5 of Three_st is
begin
process(I,T)
begin
if (T = '0') then
O <= I;
else
O <= 'Z'...
This is the only thing that i want to do.. i wanna learn VHDL. For now my biggest problems were this two, for which i ask here.I am reading tutorials, but my english is not perfect and i have some problems so i asked here.
I am very grateful for your help and advice,
thank you very much, but now i have any problem with tristate buffers :?
this is my code: entity Three_st is
port( T: in std_logic;
I: in std_logic;
O: out std_logic);
end Three_st;
architecture Behav5 of Three_st is
begin
process(I,T)
begin
if (T = '1' and I = '1') then
O <= '1';
elsif (T =...
so i can ignore this warnings: WARNING:Xst:647 - Input <din> is never used.
WARNING:Xst:647 - Input <reset> is never used. ?
I think something in my code is wrong :sad:
thanks, this is fixed, but now my RTL scheme for decoder looks like this
---------- Post added at 18:28 ---------- Previous post was at 18:28 ----------
I am newbie and dont know how to fix this... please help
whats wrong?! ERROR - Enumerated value U is missing in case.
entity dec is
port ( din: in std_logic;
reset: in std_logic;
outp1 : out std_logic;
outp2 : out std_logic);
end dec;
architecture Behav2 of dec is
begin
process(reset,din)
begin
if (reset = '1') then
outp1 <= '0';
outp2 <= '1';
else...
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