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Recent content by curty

  1. C

    AOCV Derates are not used for SDF gneration

    Is there somebody who can answer this ? This is related to C28 Technology where STA is done using PBA-AOCV. For slew & load checks, cell derates & net derates are not used. But in timing checks (setup/hold) derates are used .. What is the reason for this ?
  2. C

    DFT modes used in Si Validation

    Extest & Instest capture are the modes in STA. May be you have n't seen such scenario. Apart from this we have PBIST & TFT_Capture too. But was looking for detailed information about these .. If somebody can share then it will be helpful ..
  3. C

    AOCV Derates are not used for SDF gneration

    For slew & load checks, cell derates & net derates are not used. But in timing checks (setup/hold) derates are used .. What is the reason for this ?
  4. C

    DFT modes used in Si Validation

    Thanks for the reply maulin .. Please elaborate on ATPG & StuckAT Modes too .. Can you explain in detail about extest & intest capture too .. These are used in STA closure ...
  5. C

    AOCV Derates are not used for SDF gneration

    For slew & load checks, cell derates & net derates are not used. But in timing checks derates are used .. What is the reason for this ?
  6. C

    DFT modes used in Si Validation

    My query regarding the different mode we have in STA & DFT .. Functional Transition fault test capture PBIST Extest Capture Intest Capture Scan Shift Scan Shift Inversion ATPG Mode Stuck At Mode Can someone explain in detail. What are all these modes & what is the frequency of operation with...
  7. C

    DFT modes used in Si Validation

    Please let me know what all DFT modes are used for Si Validation. How they all correlate to the STA modes & what is the frequency is all modes ..
  8. C

    AOCV Derates are not used for SDF gneration

    For slew & load checks cell & net derates are not used. What is the reason for this ?
  9. C

    Difference between logically exclusive & mutually exclusive clocks

    In set_clock_groups what is the difference between logically_exclusive, physically_exclusive & asynchronous clocks. Please give one example . Also how it helps in PTSI
  10. C

    regarding inputs to cts

    You can use "createClockTreeSpec" for creating clk spec file in CDN . For creating spec file it will use information from SDC to create spec file ..
  11. C

    AOCV Derates are not used for SDF gneration

    Makes sense . But still whatever delays are seen in actual STA & whatever are there in SDF there will be a big difference . Should some extra margin be included in sdf for better correlation .. Also for slew & load checks cell & net derates are not used. What is the reason for this ?
  12. C

    regarding inputs to cts

    You need target skew, clock buffer list, max trans constraint for sinks , max trans constraint for buffers & max Cap too. You have some target for insertion delay, then give that too, otherwise in first pass let the tool build clock tree. Then for better optimization you need custom ignore pin...
  13. C

    How is substrate connected to ground in all cells of Virtuoso layout?

    In the well taps, there two connections one for connecting nwell to vdd & other for connecting substrate to vss ..
  14. C

    AOCV Derates are not used for SDF gneration

    I have a query regarding SDF generation. For STA , cell & net derates are used in timing closure, But for SDF generation & load/slew checks derates are not used ? What could be the reason ?
  15. C

    Why rise/pos edge flops are preferred over neg edge flops

    That right, but for neg edge flops we have to use 1@clk pin for sleep mode ... .. Zero will be used only when block is power gated & its in off state ..

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