Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
FvM - Re patent: You are absolutely correct that claim 11 didn't pass muster - it was rejected as solidly as several rounds of previous claims. Only thing that is important is the claims that were allowed in the granted patent (US patent 7,221,251, granted May 22,2007) which limited the scope of...
My dc:dc designs have used feedback from both the switch node and the output. If you look at the complete loop, the unity gain crossing is 100% of the switching frequency - that's why it oscillates. But if you analyze just the outer loop around the output node (as if the inner loop from the...
Absolutely! Under a specific set of conditions, one can substitute a delay for hysteresis in a loop like this and get equivalent results, with the delay being equivalent to the time a ramp takes to get through the hysteresis window. But change the ramp rate, and this equivalence changes. So my...
FvM is correct. A LINEAR MODEL CAN BE BUILT! The trick is what grizedale alludes to: The overall loop is an oscillator: at the switching frequency, the loop gain is unity and the phase is 360 degree. If you think about it, the oscillation cannot grow larger than rail-to-rail, as this "clipping"...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
