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Recent content by coshy

  1. C

    what create_generated_clock is used for?

    I think now the time for asking bout what create_generted_clock is used for and I found some common usages the create_generated_clock is used for the derived clock. But I'm confused that there is another "-divided_by 1" and "-combinational" options in there. If I use -divided_by 1 option then...
  2. C

    what create_generated_clock is used for?

    I expected that I could search all. but it's really hard to find it. I'm not just expecting about the create_generated_clock's syntax description. Especially, Why does "-master_clock" use 2 argument? and what does it mean? 1711010548 Thanks, I found something clues from here I think the...
  3. C

    what create_generated_clock is used for?

    I'm trying to understand about create_generated_clock. basically, create_generated_clock is defined as the following. From Here, I'm confused that what is "the get_clocks"and "get_pins" of master_clock? +-----------+ | | CLK_b ---->| |---->...
  4. C

    [SOLVED] Where is peak power on Dhrystone Gate Level Simulation?

    After Gate Level Simulation of Dhrystone, 3rd party Company successfully done for average power report to me. After job, then they asked the power peak dump duration from the Gate Level Simulation on FSDB file for checking IR-DROP. when I said a start and end point "2.5us~30us", they want to...
  5. C

    vcs compilation option "-file" does not work.

    Does anyone have the same problem compiling with "vcs -file" in VCS? Currently I am getting a keep compilation error message with "vcs -file" in vcs. -file filename Specifies a file that contains a list of path names to source files and required analysis options. You can use this option to...
  6. C

    [SOLVED] How to resolve Timing Violation in back annotation with post gate level simulation?

    I'm curious how you usually simulate in post-simulation when there is a timing violation between different clocks. Probably, if you are synthesizing, you are synthesizing with set_false_path, so you don't have the timing violation problem at synthesis. But in the actual post back_annotation...
  7. C

    [SOLVED] How to resolve Timing Violation in back annotation with post gate level simulation?

    I am still checking the same problem. I am getting timing violation now and the data of f/f is data made in different clock. Can I disable timing check when simulating between different clocks? How do you usually solve the timing violation problem between different clocks? when I check with...
  8. C

    [SOLVED] How to resolve Timing Violation in back annotation with post gate level simulation?

    Yes, and use it $back_annotation(my_sdf,...,)
  9. C

    [SOLVED] How to resolve Timing Violation in back annotation with post gate level simulation?

    From recommands, I have searched Standard Cell Librat DATASHEET. Pin D has specific requirments. setup (high ) 0.024997 setup (low) 0.034080 but when I check, sc9mcpp84_14lpu_base_lvt_c16.v there's are defined ARMSETUPTIMEandARMSETUPTIMEandAR_HOLD_TIME $setuphold(posedge CK &&&...
  10. C

    [SOLVED] How to resolve Timing Violation in back annotation with post gate level simulation?

    Thanks. Why does it make a setup violation? Is it setup violation possible that even though STA passed?
  11. C

    [SOLVED] How to resolve Timing Violation in back annotation with post gate level simulation?

    Dear All, I'm trying to resolve current timing violation in back annotation with post gate netlist simulation. Our third party Back-End company progressed STA and made SDF. As you can see the below, that is the simple SDFF register. Inputs are clk, din, reset and output is dout. Here is I...
  12. C

    [SOLVED] Can I use a Virtual clock instead of using a create_clock?

    Let me check it with your answer. But, the usage of definition virtual clock. As Far I Know, If I declare the clock with "-name" then it should work as virtual clock. So I was asking with it. I refered with...
  13. C

    [SOLVED] Can I use a Virtual clock instead of using a create_clock?

    Hi, I'm confusing that whether virtual clock declaration can use instead of real clock's create_clock. Because I came across the SDC file what there is no definition of create_clock for real clock. Basically, We use Clock Definition as the below. ################################### #...
  14. C

    Wrong timing report from all path.

    Maybe I did something wrong. Sir, I've got report_input2r.rpt Warning: cell 'R1_reg[0]' is of the wrong type. (UID-119) Warning: cell 'R1_reg[1]' is of the wrong type. (UID-119) Warning: cell 'R1_reg[2]' is of the wrong type. (UID-119) Warning: cell 'R1_reg[3]' is of the wrong type. (UID-119)...
  15. C

    Wrong timing report from all path.

    Dear All, I'm trying to make a timing report for all path which is 1. Input to register path 2. Register to register path 3. Register to output path 4. Input to output path Basically My design is RTL: module MY_DESIGN ( Cin1, Cin2, Cout, data1, data2, sel, clk, out1, out2, out3); input...
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