Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Just to be sure:
-do you mean the field monitors which evaluate the field in 3D (or 2D) or the field probes which measure the field in just one point (because i am interested in the field monitors)?
-how can i plot all the field monitors on the same graph? what command should I use?
It does not really help with my problem, since i need a specific surface, not points.
I have found a macro which automatically puts field monitors for each frequency I need. There will be about 2000 monitors, since these are the requirements of my project (between 1-3 GHz).
Afterwards I would...
To make it a little bit clearer:
I want to put a EM source at some distance (1 meter) from the box and make a frequency sweep to see the 3D model of the emission distribution in the box, in order to know where to place some sensitive components.
Hello,
I have a question regarding the CST MWS program, and don't seem to find
the answer in the tutorials/ forums.
I want to test the imunity of a box (shield) - which will contain a PCB -
in some frequency area (1-3 GHz), so that to know where to place it.
My question is how can I make this...
I simulated your program - timing simulation (after synthesis and routing) and it works just fine.
The duty cycle shouldn't matter. Problems may occur only if your clock isn't stable, or if the duty cycle varies a lot. Even so you should see a normal sequence (0,1 ,2) but the time is stays on...
Thanks for your post, it was really what i needed. I managed to figure it out just about some hours ago, and wrote about the problem in more detail here:Re: trimming of wanted (useful) signals in XILINX ... - Xilinx User Community Forums
Thank you for your reply. I would also be interested why does the synthesizer "optimize" my code in such a way. Maybe I'm writing my code somehow wrong.
Could anyone point some parts in my code that need improoving or revision?
I'm implementing a finite state machine to count some events.
The pre-synthesis simulations works fine, but the post synthesis doesn't. Im sure it's because of the trimming:
Any help would be appreciated.
entity fsm_moving_object is
Port ( CLK : in STD_LOGIC;
A : in...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
