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vhdl edge counter
it's not the synthesizer, it's the target
look at this simple code: (sorry, I'm a verilog guy)
always @(posedge clk or negedge clk)
x = x + 1;
It is synthesizable and it does work in some CPLD's like XC2Sxx (Xilinx)
The target you point the synthesizer to must have...
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