Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dear All,
I have a question on delay path fault test pattern generation. As we know, to test the delay path fault we need two test vector, v1 and v2. V1 is to initialize the circuit, and V2 applies to the circuit to generate a transition on the path under testing. Given a path under testing...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
