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Recent content by coolsaurabhsonu

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    Phase Detector Design for Delay Locked Loop

    Hi All, I have a very basic question, is the locking time of loop depends on the types Phase detector, means if i use PD using static logic (NAND gate) or PD using Dynamic logic(TSPC), which will have better smaller locking time and why(reason). please replay. Thanks
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    Delay Locked Loop Design

    Hi All, can anyone please help me regarding the false locking in delay locked loop. and how we can avoid this false or anti-harmonic locking. thanks
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    Delay Locked Loop Design

    Hi Zeker, while doing corner simulation (slow-slow) and (Fast-Fast) corner i saw that the control voltage (output for Charge pump and loop capacitor) is oscillating(oscillation is around 200mV). so i increase the loop capacitor . and after that it settles down. so my concern are : 1. Is this...
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    Delay Locked Loop Design

    Hi, I am working on delay locked loop design. My concern is related to loop filter capacitor, does loop capacitor can cause loop stability issue. please help in this regards.
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    Symmetric load in Voltage controlled delay line

    Hi All, I just want to know about symmetric load, how it works. Why it is termed as a symmetric load , even it's not at all symmetric across its voltage swing. and it's not even acting as a linear resistor. but people are reporting this as a resistor which can acts as a variable resistor for...
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    Replica Bias Voltage Controlled Delay Line Design

    Hi, i am working on Voltage controlled delay line (VCDL) for Delay locked loop(DLL). i started VCDL design using Replica Bias which is given in razavi book(Fig attached). as mentioned in book, For VDD= 3.3V , i kept VREF = 2.1V , so that to have swing of 1.2V. And kept both M3 and M4 in linear...
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    vco with replica biasing for pll

    Hi All, can you please help me in designing Maneatis delay cell for DLL. i have few queries : 1.How the Symmetric load works. 2.With linear load how the dynamic supply variation improves. 3.How the delay varies with control voltage. 4.In Maneatis delay ,the swing is also varying with VCTRL ...
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    why the differential buffer stage in John Maneatis's paper has good supply rejection?

    Hi, Do u have the detailed analysis of the symmetric load, means how it's work and how its improving the power supply noise. why its required to have a linear resistor in buffer load. thanks
  9. C

    bias circuit and differential buffer stage design

    Hi, i am working on this delay cell for DLL design. i just want to know how the symmetric load works. and how a linear load have more dynamics power supply rejection. if you have any good reference material, can you please share with me. thanks
  10. C

    class B push pull power amplifer design

    hiiiiiii I have to design a CLASS B push pull power amplifer. for the operating frequncy = 402 MHz, it should able to transfer 500uwatt power to 50 antenna. i am using Vdd =1.8V using calculation i got RL=810 ohm. i.e RL = Vdd ^2 /8*Pout = 810 Ohm. so i need a matching networt that can see...
  11. C

    The feedback resistor on a CMOS inverter

    hiiiiii LvW.. i need to know about self biased inverter ( output node ir drain of PMOS and NMOS is connected to Common Gate via a resistor) , i have gone through some paper in which they are using that as a buffer amplifer and according to paper self biased inverter reduces second harmonics...
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    Power amplifier (self biased inverter)

    hiiiiiiiii all, i am working on MICS band application , and I have to design a Power amplifier that can deliver 500 uwatt power to antenna(50 ohm). i have gone through some IEEE paper and i found that most of them were using Class AB power amplifier which is driven by a self biased inverter...
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    class AB power amplifer output power Response time

    hiiii i m working on CLASS B Push pull power amplifier frequency Range 402-405MHz , i have to design a power amplifier that can deliver 500uwatt power to 50 ohm load. the thing want to know is 1. when i m doing transient analysis and calculating power at 50 ohm load ,the power at load is...
  14. C

    class AB power amplifer output power Response time

    hiiii i m working on CLASS B Push pull power amplifier frequency Range 402-405MHz , i have to design a power amplifier that can deliver 500uwatt power to 50 ohm load. the thing want to know is 1. when i m doing transient analysis and calculating power at 50 ohm load ,the power at load is...
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    class AB power amplifer output power Response time

    hiiiii all, i am working on Class AB power amplifer, problem is that the Output Power at load settles constant after long time, how to improve that response time.
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