Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by coolkwc

  1. C

    Verilog problem with building shift register which can have parallel or serial input

    Verilog problem module shiftregister(parallelin,load,w,clock,Q); parameter n = 32; input [n-1:0] parallelin; input load,w,clock; output reg [n-1:0] Q; integer k; always@(posedge clock) if(L) Q<=parallelin; else begin for (k=0;k<n-1;k=k+1) Q[k]<=Q[k+1]; Q[n-1]<=w...
  2. C

    Need help on my work...FSK modulator by using MATLAB

    fsk matlab Bro, i figured out what should i do adi... Actually my work quite easy only, let say if i assigned bit 0 as 1000hz and 1 assigned as 1400hz, if detect 1, output sine wave of 1000hz, else if detect 0, output sinewave of 1400hz, and then just add this two wave then the FSK is...
  3. C

    Need help on my work...FSK modulator by using MATLAB

    matlab program for fsk i have been requested to simulate the FSK modulator by using MATLAB...i have no idea how to start the work... OK, i have study about the ASK and FSK....i know the FSK can produce by combined the ASK waveform and added together with summing amplifier, how true is my...
See more

Part and Inventory Search

Back
Top