Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by cooldog

  1. C

    Any example of PLL simulation with AHDL in spectre simulator

    Re: Any example of PLL simulation with AHDL in spectre simul There is a sample for PLL in Cadence's samples.
  2. C

    What simulator is better HSPICE or SPECTRE ?

    Did any one heard of ADiT from EverCAD? It said it is a fast spice simulator and can compete to Hsim from Nassda. Now Nassda is dead, can it occupy the position? Tell me any information if any one knows about it?
  3. C

    Is Cadence CMI open source?

    cadence cmi Is CMI (Compiled Model Interface) from Cadence public source? I did not see any information about the interface. If I want to define a customized model, can I use CMI to do it by myself? Or I need Cadence's help?
  4. C

    Is there any simulation tool free for mixed-signal

    Co-simulation? Try ADiT-VPI from EverCAD. It works in solaris, linux, hpux even Windows.
  5. C

    How to apply b to a after a time delay: a<=#10b in Verilo

    Re: About verilog-A question How about this? @(timer(td)) begin a = tmp; tmp = b; end
  6. C

    Besids modelsim which tool can open *.wlf ?

    how to open .wlf The waveform viewer vandor should accept WLF format if he get the interface library from Mentor Graphic. As I know, Mentor provide the API library but I don't know if it is free. Some viewer vandor like sandwork, maybe can do this work.
  7. C

    verilog-a question (about system task $fopen)

    verilog fopen There is no "a" (append) option for $fopen in Verilog-A. So your problem is veru difficuit to solve in Verilog-A language. But it is strange why you need to keep all data for each simulation. Maybe you need to change your design to do the simulation at one run.
  8. C

    questions in verilog-a,

    Hi there, Verilog-A is not well defined language. There is no bus concept for analog part. If the vador tool supports bus port like svensl said, it should work. I don't know if Cadance Spectre support bus port issue. But some other tools support, like hsim, adit ... So this is the vador...
See more

Part and Inventory Search

Back
Top