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Hello, I keep getting the above error when attempting to run Assura DRC on a simple layout of an inverter. I am using IBM 90nm technology.
Additionally, here are some of the errors in the Cadence terminal:
*No tech lib map file 'assura_tech.lib' or 'pvtech.lib' found.
*No rule sets can be...
Hello, I Keep getting the "Failed to build VDB. Cannot submit DRC run" error when I am trying to run Assura DRC in my layout. In the cadence log, it shows that many layers are undefined as well. We are pretty sure it's because we are using Assura version -614 and layout version -615. Is there...
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