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If I recall correctly, you cannot dump out an EVCD file using Verilog HDL - the simulation tool has the capability to do that. Which simulation tool are you using?
Which exact Cadence tool are you using? Do you know *why* the constraints file is not found?
Did you synthesize the circuit with the Cadence synthesis tool called Genus?
Cadence's Innovus Place & Route tool has the following command
timeDesign -postRoute
As you can see without enough...
You might want to see if you have access to a newer version of the dc_shell tool as the one you are using is nearly 8+ years old. Can you confirm the dates of the DW library you are using and the tool version?
TOOLs and Tech: Questasim 10.5c-2 / Synopsys design_vision I-2013.12 / STM 65nm
I recall correctly, some time back when using this particular library that the simulation Verilog cell library .v file did not match logically the synthesis liberty .lib file used for synthesis when doing logic...
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