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Recent content by circuitking

  1. C

    2-stage opamp gain?

    There is no way to remove a post. Yes your are right, that is the answer gm = 2Id/Vov
  2. C

    Analysing below circuit

    Thanks for the good explanation. You mean Cslow provides filtered reference to the inner FVF loop? is this the Vset?. filtering due to cslow and output resistance of opamp? I am looking for the equations for gain and bandwidth of the inner loop and DC gain and bandwidth of the outer loop in...
  3. C

    Analysing below circuit

    Could you tell how the C1 impacts the design? What happens if there is no C1
  4. C

    Analysing below circuit

    Hi all, I would like to analyse the circuit. how to draw the small signal model for the two loop circuit below. How to calculate the pole frequencies from each loop How to calculate the PSRR of the circuit How do I determine the value of the C1 and Cslow so that the circuit is stable? What...
  5. C

    PSRR in bandgap reference

    Hi all, the below figure2 is PSRR of a bandgap reference (Vbg/Vdd). In Figure 1 Could you tell what do I need to do to push that floor at low frequencies to more lower values? say -90 dB What do I need to do to push the high frequency behavior to higher frequencies? for ex. the constant low...
  6. C

    What is the avg current flowing from B to A.

    Hi all, I didn't understand what is the answer. Is it CVf?
  7. C

    Books for SERDES tranmitter driver with pre-emphasis

    Hi all, I spent a lot of time searching for a book that gives me overall understanding on the SERDES transmitter driver design with pre-emphasis/FFE FIR filter equalization. I only found few papers and some slides in the internet. Please let me know if there is any good material to design the TX...
  8. C

    What is the avg current flowing from B to A.

    Hi can anyone tell me what is the avg current flowing from B to A in the attached figure. I just gave some random values for voltages and capacitance. Please tell how to theoretically find it.
  9. C

    How to generate a pulse signal with varying pulse width in Virtuoso

    Dear all, I would like to generate a pulse signal with varying pulse width with in the given time limits. The center of all these pulse should be in the same place on the x-axis. I used variables for delay time and pulse width for Vpulse component in analoglib and did a parametric analysis but...
  10. C

    Plotting signal by uploading a file to virtuoso ADE-L

    Thanks for the answer. I have below questions 1.The Psf DB is generated after the simulation has run but I want to give the net names before the simulation and plot 2.I though after the simulation has completed I will edit the tran.tran file and open the psf db, but I can't open tran.tran file...
  11. C

    Plotting signal by uploading a file to virtuoso ADE-L

    Hi, I want to plot signals from ADE-L not by adding outputs to it but by attaching a file to ADE-L? I know this can be done with Ocean scripting but can we do it with GUI itself just like setting initial conditions in .scs file. Thanks
  12. C

    How to set initial condition for a net in the netlist

    Hi, this is my net (net020<7>). This is the hierarchy in my schematic before extracting parasitics, I48.IR<1>.IM<7>.IC24<3>_net020<7>. Block IC24<3> is inside the IM<7> block. But I got errors because of . and <, when I used I48.IR<1>.IM<7>.IC24<3>_net020<7> expression for the net. Is this the...
  13. C

    How to set initial condition for a net in the netlist

    Hi, when I have done the simulations with schematic. I can set initial conditions using ADE->Simulation->Convergence Aids->Initial Condition. Now, I replaced the schematic with its parasitic extracted net-list. So I can't access internal nets by descending into the schematic. How do I set...
  14. C

    Delay element in feed forward equalizer (FIR Equalizer)

    To design 3-tap FIR equalizer.
  15. C

    Delay element in feed forward equalizer (FIR Equalizer)

    Hi All, what should be the delay element in FFE? Is it a flip-flop? How do we decide whether to use a flip-flop or some other circuit for providing delay in FIR filter equalizer. Is there any good book on SERDES, FIR filter equalizer design?. Thanks
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