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We need to see how many of these companies will stand through the recession. Few companies in this list have already closed vlsi divisions and few of them got sold to bigger companies.
cadence+post simulation
Yes, an ideal current source means that it gives out constant/fixed current irrespective of the potential difference across it. Potential difference across the ideal current source does not imply its resistance.
This is my understanding. Correct me if I am wrong.
cinch
ldo without output capacitor
Hi,
Output capacitor of LDO, also called load capacitor can be either external or internal to IC. Depending on its value, it sets one of the pole of the LDO along with the output impedance of the LDO. Load capacitor is also important to suppress the LDO output...
Hi,
SF / FS are few MOSFET corners to check the behavior of the circuit when NMOS and PMOS have different strengths, like for SF - Slow NMOS, Fast PMOS; FS - Fast NMOS, Slow PMOS.
Monte Carlo simulation gives the effect of mismatch between two identical transistors (like input pair of...
You have to do PSS (Periodic Steady-State) analysis if you have to do temperature sweep simulations. Also, to check stability, you have to do PSS and PAC (instead of conventional DC-AC simulations). For this you need Spectre-RF license, can not be done with spectre.
Re: about opamp design
For opamp with high accuracy, it should have high gain.
For opamp with high speed, it should have large bandwidth.
But for an opamp with given architecture and current, the Gain - Bandwidth product is constant. Thats the trade-off.
cinch
Re: about zero and pole
Frequency Domain:
Presence of a pole makes the gain to roll-off (falls) @ 20db/decade. If a pole is present at origin, the gain plot begins with 20db/dec roll-off. If there r 2 poles at the same point, gain rolls-off @ 40db/dec and so on. Presence of a zero increases the...
Re: Geometric-Harmonic Mean
hi,
check the link - https://en.wikipedia.org/wiki/Harmonic_mean
Harmonic mean can be used in programs that calculate or estimate the speed of a missile or two trains, where in some decision has to be made by knowing the average speed of the object
for...
Hi,
Yes... if i put simple 2 stage RC filter whose time constant is same as (or more than) switiching frequency, then i get the average of the input signal. But the value of R needed is about 1Mohms and the settling time of this ckt is 1.5ms... This is not feasible. Ckt should be up in atleast...
Hi,
I know that clk frequency should be much higher than signal frequency only when u want that signal at output without distortion. But in my case, I dont want the exact signal, but i want the average (mean) of the signal. For this to happen, clock frequency must be lesser than signal...
Hi,
You can not do AC simulation to check for phase margin using cadence, just like u do for other circuits. For PLL, u write transfer function (TF) for each block, say
for PFD - 1/2pi
for VCO - Kvco/s (integrator)
Divider - 1/N
for LPF - 1/sC/R+1/sc etc etc.
Write down open loop TF - G(s) for...
Hi,
1pf is ok, u can go for lesser value also upto 500fF. Only thing is for the given frequency, if u use higher cap, u have to spend more current to charge. So lesser the cap, lesser is the current needed, assuming good process like TSMC or UMC. It depends on ur current spec. Also, its not...
Hi,
I am designing a switched cap LPF to average out a square wave. The frequency of square wave is 10kHz. The magnitude of the input square wave varies. The circuit should give an output which is the mean of +ve and -ve amplitude of the square wave.
For eg: If input square wave is varying from...
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