Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by Ciaran

  1. C

    Error message using Modelsim in Linux

    Firstly, thank you all for your kind help. nand_gates, I tried the update you suggested for the test bench but unfortunately this had no effect! I have attached the code for radix2_cell_array. I originally thought that the problem may have been with the Signal_Assign process in which I have...
  2. C

    Error message using Modelsim in Linux

    Hello All Thank you in advance for kindly agreeing to help me with this, as I have been stuck for quite some time. Basically, I am receiving the following error message when using Modelsim in Linux: ** Error: (vsim-3601) Iteration limit reached at time 0 ns. I have read previous articles...

Part and Inventory Search

Back
Top