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Hi all,
I need some help on the convention naming of cadence library.
(1) I have found that some companies use only lower case letter (small letter word) to name their Library Name, Cell Name, Schematic Name. Any reason?
(2) How about the Port-name and Net-name inside the Schematic?
I've...
Re: guard ring
hi surianova,
if u hav a noisy block and want to prevent it to effect other block, better split it.
if your block's gnd impedance much lower than guard ring, then guard ring will be useless but this normally not the case.
if your chip has enough pads, split-it is the ideal...
hi all,
i'm choosing a POWER SUPPLY equipment for test and measurement on ANALOG CHIP. please give me some advise on the SPEC, thx in advance.
1) what is the MAX "ripple & noise" acceptable for analog chip ? 5mV rms & 3mA rms ? 10mV ptp ? or ?
2) line regulation constant voltage & current ...
hi, i have a few questions here please help, thanks in advance.
Please check this 1 stage op-amp:
1) simulation gives differential voltage gain Av=36dB which is too far away from hand-calculation 58dB, why ?
NOTE : with current mirror load, Av=gm (Ron || Rop), gm depends on Ic (≈56uA) which...
hi all,
(1) what is line regulation means in bandgap ?
(2) temperature coefficient TC's unit in ppm/C, ppm is part per million for what ? doping concentration ?? or ... ??
i only know TC for mV/C.
thanks
how to determine the absolute max rating value for analog chip ?
is it partly from the spec for the packaging ? what about other criteria ?
thx in advance.
Re: flash memory
briefly:
(1) eeprom - non-volatile for storing data, can erase bit by bit and re-write
(2) flash - function exactly similar to eeprom, but can only erase by page. size much smaller than eeprom, that's why market tuning to flash when page-erase getting smaller and smaller...
Re: Transistor HFE
transistor with
(1) smaller Wb (base width) or
(2) higher ratio of emitter to base doping densities
will have higher βf or hfe.
from (1), it explain why npn has higher beta compare pnp. Wb of npn is fixed by process, Wb of pnp depends on how wide the designer draw it...
hi selvaraja,
u can use resistively loaded diff pair actually, but u will hav lower output impedance and voltage gain.
But this can be improve by using degenaration below the diff pair.
i do not know abt any other architecture, if somebody does, pls tell.
thx.
rgds,
chu
hi holddreams,
Vref=KVt + Vbe ; K a function of resistors and bjt size
if Vt TC=+0.085mV/C and Vbe=-2mV/C, we find K which will cancel out each other. let say K=24
assume we increase temp from 25C to 60C, delta is 35C,
for Vbe--> decrease abt 70mV (from 35×2) from original
for Vt--> increase...
hi,
wjxcom is right abt same side of single-ended-diff-amp's output is the +ve terminal. If u have the output connected to common source, then refering to output of that common source, the input terminal must be switch (Davood is right), this is what happen in 2-stage-op-amp.
rgds,
chu
hi ambreesh,
it depends on the process whether the fab can supply u that kind of transistor.
u hav to check the beta vs Ic curve whether u can get an appropriate beta with that amount of Ic. From what i know, Ic of around 10uA is possible but then create difficulty on BGR circuit.
rgds,
chu
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