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What are you using to synthesize? Xilinx ISE?
You can use ModelSim to simulate. It's very easy to use and will allow you to debug. There must be some issues with the logic or how some signals are routed. Simulate the entire top level design and make sure each signal is the correct value it...
I didn't see that P is an output in your top level design. You need to declare a signal that can be used internally that you would then set P equal to. You cannot read an output signal.
It seems like this is the first time you worked with structural VHDL design. I suggest you read: VHDL...
If you are taking an output from stage0 and you want to manipulate it in some way before you feed it to stage1, then you can take the signal z( 3 downto 0 ) and use it with an intermediate signal to produce the input for the next stage.
Say you are using the statement ztemp(3 downto 0) <= z (3...
Temporary signals are your best friend.
simply use another
signal temp : std_logic_vector( 3 downto 0 );
temp <= n( 3 downto 1 ) & P( 1 );
The & signal concats signals together.
Exactly! The input must be the same length as what you describe the component to be. The synthesizer will throw an error if a 2 bit std_logic_vector is sent into an input that expects 3 bits.
Good luck and let me know if you run into any other problems!!!
stage0: fulladder4 port map (x(3 downto 0)=>k(3 downto 0), y(3 downto 0)=> l(3 downto 0),ztemp(3 downto 0)=>(z(3 downto 1)=>n(3 downto 1), z(0)=>P(1)), Cout=>Cout1);
This is wrong because in the full adder:
z: out std_logic_vector (3 downto 0);
so instead use:
stage0: fulladder4 port map (...
I will not write all the code for you, just a small snippet but from my understand it seems like you are trying to divide a clock using a counter. This would work as follows:
If you want to divide the clock by four for example you would use a signal that could count to 4 and use a comparator...
Posting your code so others can see before I answer. Your code is as follows:
--create of multiplier 4bit X 3bit
library ieee;
use ieee.std_logic_1164.all;
--declaratio of the multiplier entity
entity multiplier4X3 is
port ( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (2...
What kind of errors are you getting? I need more information in order to help you. Is your design properly reset? How are you multiplying? It would help a great deal if you posted your code.
Thanks
I am currently using a virtex-5 with a 500MHz differential clock that is DCM'ed down to 250MHz for the logic, and 125MHz for the powerpc/bus/etc. I believe that xilinx virtex-5 powerpcs can run up to 250MHz (good luck meeting timing though) and the fabric can run up to 500MHz.
Hey,
It is extremely simple. Instantiate IOBUFDS for inout, IBUFDS for input differential buffer, or OBUFDS for output differential buffer.
Reference: **broken link removed**
Also remember to add unisim library to your vhdl/verilog file
PLC's are expensive, usually much larger than an embedded system, and are less robust. PLCs are usually designed to be used for testing/automation of a single product (cars), where as an embedded system can be easily modified to work with multiple projects without having to change any circuitry...
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