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Recent content by chinito

  1. C

    S parameter simulation in cadence

    s parameter simulation Hi, Is there a tutorial out there that explains simple S-paramter simulation on cadence i.e. what kind of voltage source with port number and termination should be used, what analysis to run, how to plot S11,S12,S21,S22 etc? many thanks in advance.
  2. C

    What is the future for CMOS Analog IC Designers ?

    I think power management IC are going to be big. Just look at job openings these days. It's hard to find designers (Analog) who could design power management ICs. That's just my opinion.
  3. C

    technology parasitics

    If you want to calculate capacitance, say between M1 and M2 running parallel, then you need to consider two components: Area and fringe. In smaller geometry process, fringe could be dominant. So you're looking at (M1,M2) area multiplied by capacitance per unit area between M1, M2 PLUS perimeter...
  4. C

    how to measure inductance with s-parameter?

    Thanks Jian.
  5. C

    Can I connect guard ring or chip guard ring to the ground ESD of the chip?

    Re: guard ring I've never seen it done before.
  6. C

    Problem with Cadence Virtuoso Analog design environment.

    how to operate the cadence virtuoso analog design you're gonna have to change your .cdsenv file and go with the default plotter (ADE) than wavescan.
  7. C

    What are the conditions under which latchup in an IC occurs?

    Re: LATCHUP In a cmos process, you always endup with a pair of PNP and NPN. Latchup occurs when betaN*betaP > 1.
  8. C

    how to measure inductance with s-parameter?

    Hi, I want to measure inductor on network analyzer. How do I go from S-parameter to inductance? How does one measure leakage and magnetizing inductance through S-parameter? Thanks.
  9. C

    rdson of PMOS increases a lot w/current but NMOS's doesn't?

    I'm using 0.5um process and ploting rdson of PMOS and NMOS (10mm each). Rdson of PMOS increases a lot with current while that of NMOS doesn't. I wonder what's the explaination? thanks.
  10. C

    how to generate 4 phase clocks (90 degree offset)

    I need to generate 4 phase clocks. what kind of circuit should I use? Thanks.
  11. C

    how to design variable f variable D oscillator

    vco xr2209 I need to design variable f variable D oscillator. Any suggestions where do I start? Thanks.
  12. C

    benefit of folded cascode opamp

    folded cascode self compensating + good input CM range, output CM range decoupled from input CM. - current runs in third branch - pole at folding node
  13. C

    how to reduce parasitics at switching node of the switcher?

    Hi, How do I reduce parasitic cap at switching node of the switcher layout? How to layout power fets? If we're stuck with the parasitic, can we do something about that cap (tuning maybe?) Thanks. Chinito
  14. C

    how to size FET for 2A for DC DC converter?

    I'd like to know how do you size say a PFET for 2A of current in a DC DC buck converter?
  15. C

    good books on DC-DC converters for beginners?

    Could people experienced in DC-DC converter design please list good books for beginners like myself. Thanks.
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