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Recent content by chihom

  1. C

    modelsim $init_signal_spy in the mix-mode with verdi

    init_signal_spy I run the $init_signal_spy in the verilog top level to see the hierarchy cross the vhdl code segment. then I use the novas lib modelsim_fli6xx.so to link with modelsim to dump the mix-mode simulation result. but the $init_signal_spy function always error when modelsim...
  2. C

    Advanced digital intergrated circuit-berkeley 8,9,10,11,12

    the other parts? where are the others...? :?
  3. C

    Is there a tool similar to debussy ?

    debussy debussy 5.3 feature Verilog 2001 Support VHDL 2000 Support Clock Domain Extraction Multiple Clock Analysis PrimeTime Timing Report Open Vera Assertion (OVA) Support FSDB Dumping and Viewing
  4. C

    Opinions on VCS 7.0 software

    I think the vcs 7.0 will support more tools than older version... ex : vera , formality ...etc , and they don't support NT version...
  5. C

    D/e/b/u/s/s/y 5.2 - doesn work, why?

    The debussy is a debug tool to view the HDL and schematic in design and it suport PLI to link simulator to extract waveform to debug .. 8O
  6. C

    What kind of bugs has synopsys dc ?

    the synopsys 2002.05 sp2 has a bug.... we return back to use 2001sp2 version to guarantee it... :(
  7. C

    Is there a tool similar to debussy ?

    debussy 5.3 had announced.... 8)
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