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Reply on your first thing: the simulation is not ok. At 800 ns it shows a high signal and i expected it to be at 1500 ns.
On your second thing: I will look into it.
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Ok thx for the answers!
4. My teachter at my school never taught us to use testbenches before so i wouldn't...
Well I'm still learning it and this how a teacher taught me it. Yes, I'm dutch haha I don't speak afrikan, but I do know the similarities. Ok i will look up into vhdl testbenches then maybe it will work out better
Hi everyone im still learning to use vhdl and FPGA. I wanted to try to make a lifo system and this is the code I made:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY lifo_datapath IS
PORT
(
clk : IN std_logic;
d_in : IN std_logic_vector...
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