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Recent content by chenliy

  1. C

    EDA software license server problem

    cannot connect to server eda Who can help me? Thanks!
  2. C

    EDA software license server problem

    e.d.a cannot connect to server I started EDA software license server, but my computer showed "lmgrd is not running: Cannot connect to license server (-15,570:111 "Connection refused")". My OS is linux AS4.0. What is happened? Why is "Cannot connect to license server "? Please help me. I typed...
  3. C

    ADC simulation testing using Verilog model for a block

    Re: ADC simulation testing You could connect the input of DAC with the output of ADC.
  4. C

    Hspice simulation program

    bg21359 is right. "internal timestep too small in transient analysis" is a complex problem. You can see the book "The Designer's guide to SPICE and Spectre" by K. S. Kundert. It will help you.
  5. C

    Average Current , RMS current ?

    I think you could choose Average current. Because RMS current is Root Mean Square current.
  6. C

    How to extract the output at each 10th clock cycle in a SAR ADC simulation?

    Re: SAR ADC simulation I think that if you takes 9 clock cyles to finish one conversion, the conversion is not enough. You must use the faster clock.
  7. C

    Is it possible to simulate DNL and INL for a 10-12bit ADC?

    Re: Simulate DNL and INL You can refer to Page 662 (Testing of ADCs) in CMOS Analog Circuit Design (Second Edition). The author are P.E.Allen and D.R.Holberg. ISBN: 7-5053-7758-2
  8. C

    Any good Integrated Filter design tool?

    Matlab or ADS for you.
  9. C

    Is it possible to simulate DNL and INL for a 10-12bit ADC?

    Re: Simulate DNL and INL pablomilanes, I use AMS simulation. AMS means Analog-Mixed Signal, that is to say Spectre-Verilog simulation. Yes, matlab is used with system simulation. For a top simulation of an ADC, the paramenters needed to simulate are static parameters (INL,DNL,Full...
  10. C

    Glitches at the output of ideal dac

    The Btrend's saying is right.The fellow is my ideal 10bit DAC with Verilog-A language. `include "discipline.h" `include "constants.h" `define NUM_DAC_BITS 10 module d2a_ideal_1 (clk, din, vout); input [`NUM_DAC_BITS-1:0] din; voltage [`NUM_DAC_BITS-1:0] din; input clk...
  11. C

    Is it possible to simulate DNL and INL for a 10-12bit ADC?

    Re: Simulate DNL and INL I have finished a 10bit 2MHz-sps ADC. I put the output of ADC into the input of DAC. The DAC use Verilog-A language. The logic part of ADC, registers, flip-flops,clock generation etc., use verilog language describing. The simulation uses one day to get INL and DNL...
  12. C

    Glitches at the output of ideal dac

    I think that the difference between the clock of ADC and 10bit ideal DAC caused the glitches. The time of ADC's sampling and conventer affect clock. The clock of ADC and DAC are dissimilarity. The glitches wae not affect accurancy of ADC.The time of the glitches was very short ((1/10)*sample...
  13. C

    Automating the Simulation Process. (Spectre, Verilog-A)

    simulation verilog spectre I think you can use variables for VPWLF sources and sweep the variables.
  14. C

    How to simulate Bandwidth and Phase Margin of a PLL

    Can i use Cadence's tools simulate Bandwidth and Phase Margin of a PLL?How can I do it?
  15. C

    How can I do the DAC's DNL&INL simulation?

    You can use verilog-A for ideal ADC.
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