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Recent content by cheney

  1. C

    Simple verilog question

    0, becasue verilog definition
  2. C

    What does "WRAPPER" in ASIC refre to?and what does

    in my opinion, warpper is, if we have a AXI interface, but i don't want all AXI transfer are to AXI INTERCONNECTION, and some of AXI transfer should go to another bus depending address, so i need design a wrapper to seperate AXI transfer to different destination.
  3. C

    Exercise problems in FSM

    do you think FSM is the best way to design a circuit? i don't like FSM very much.
  4. C

    What's the best VHDL/Verilog/SystemVerilog editor?

    notepad++ plugins systemverilog vi is my favourite.
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