Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi
i got some transition violations after postrouteopt..but they were kind of spare cells..how to fix them if they mentioned dont touch in libraries? what's the location i could find spare cells in libraries?
Thanks,
chandra.
hi
after i ran CTS, i got setup violations with negative slack of 5ns. after CTSopt step, i got setup violations with negative slack of 2ns. can anyone suggest how to clear these setup violations in CTSopt?
Thanks,
chandra.
hi
i have 3 memories and placed one side of core area.i need to place them inside the core area?can anyone suggest how to place them inside core?
Thanks,
chandra
hi
i have LIBS,sdc,netlist,IO file. how would i know how many memories were there in my design? where i need to check for this? can anyone tell how to place macros during floorplan?
Thanks,
chandra.
hi
can anyone tell how to fix drc violation after done with post routing? i got one M1 spacing error..how to find the location of error in the layout?
also i got lvs errors like missing port vss on net: vss
how to clear lvs error too
Thanks,
chandra.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.